Advance Program


Follow this link for a detailed schedule including abstracts of all papers and posters
 

    CONFERENCE-AT-A-GLANCE

Wednesday, September 9

Registration
7:00 a.m. -
5:00 p.m.

 

Plenary Session
8:30 a.m. -
11:55a.m.

Opening Remarks:
   Sakir Sezer, General Conference Chair
Technical Program Overview:
   Andrew Marshall, Technical Program Chair
Keynote Presentation:
  Hermann Eul, Member of the Management Board, Executive VP Sales, Marketing, Technology and R&D,
Infineon

Plenary Presentations:
James O’Riordan, Chief Technology Officer & VP Corporate Development
Silicon & Software Systems Ltd.

  Liang-Gee Chen, Professor, Department of Electrical Engineering,
Deputy Dean, Office of Research and Development,
National Taiwan University

11:55 a.m. -
1:10 p.m.

Lunch

Technical Sessions
1:10 p.m. -
3:15 p.m.

WA1:
FPGA Design Methodologies

WA2:
PLL and Clocks

WA3:
Reconfigurable Architectures

3:30 p.m. -
5:10 p.m.

WB1:
A/D Converters

WB2:
Embedded Systems, Multi Core, and Embedded Memory

WB3:
Low-Power Circuits and Architectures

6:45 p.m.

Transportation to Parliament Building (provided)

7:30 p.m. -
9:30 p.m.

Reception
Parliament Building, Stormont

Thursday, September 10

Registration
7:30 a.m. -
5:00 p.m.

 

Embedded Tutorials
8:00 a.m. -
10:00 a.m.

Embedded Tutorial T1:
Designing Multi-Processor
Systems-on-Chip

Embedded Tutorial T2:
Microwave IC Design for Broadband Receivers

Technical Sessions
10:20 a.m. -
12:00 a.m.

TA1:
Circuits for RF and Wireless

TA2:
NoC Power and Data Flow Optimization

TA3:
Design for Testability and Verification

12:00 noon. -
1:30 p.m.

Lunch with Poster Session

Technical Sessions
1:30 p.m. -
3:35 p.m

TB1:
Analog Circuit Techniques

TB2:
System Level Design for Manufacturing

TB3:
Data Processing Architectures

4:00 p.m. -
5:30 p.m.

Panel Discussion:
Containing complexity: Keeping the costs of SoC design under control

7:00 p.m. -
10:00 p.m.

Drink Reception and
Banquet Dinner

Belfast Waterfront Hall or Wellington Park Hotel

Friday, September 11

Registration
8:00 a.m. -
3:30 p.m.

 

Embedded Tutorials
8:00 a.m. -
10:00a.m.

Embedded Tutorial F1:
Design in the nano-scale Era: Low-Power, Reliability, and Error Resiliency

Embedded Tutorial F2:
Introduction to the SystemC AMS DRAFT standard

Technical Sessions
10:20 a.m. -
12:00 noon

FA1:
Low-Power Design Methodologies and IP cores

FA2:
NoC Design Tools and Digital Signal Processing

12:00 noon -
1:30 p.m.

Lunch (on your own)

1:30 p.m. -
3:35 p.m.

FB1:
System Level Architecture Exploration

FB2:
Imaging and Video Processing

3:35 p.m.

Conference ends